Microprocessors and Interfaces: 2021-22
Lecture 24 : 8086 Bus Cycle and
Loop Delay Calculations
By Dr. Sanjay Vidhyadharan
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Bus Cycle
3
Bus Cycle
4
Bus Cycle
Has more than 1 Machine Cycles
5
Bus Cycle
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MACHINE CYCLES OF 8086
1.Opcodefetch cycle (4T)
2.Memory read cycle (4 T)
3.Memory write cycle (4 T)
4.I/O read cycle (4 T)
5.I/O write cycle (4 T)
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Memory Write Operation
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Memory Read Operation
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OPCODE FETCH MACHINE CYCLE
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IO Write Operation
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IO Read Operation
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Instruction Cycle
Time taken by processor to execute an instruction- specified in terms of
no. clock cycles needed to do it.
•
Once instruction is fetched and ready to be executed, then it can be
decoded and execution can be set.
•
Fetch-execute cycle can be divided into 6 stages
– Fetch instruction
– Decode instruction
– Calculate operand address
– Fetch operand
– Execute instruction
– Write/store result in memory
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FETCH CYCLE
Rules to identify number of machine cycles in an instruction:
1. If an addressing mode is direct, immediate or implicit then No. of
machine cycles = No. of bytes/Word.
E.g. INC AX 40h , PUSHF 9Ch , POP AX 58H
E.g. MOV AX,BX 8BC3h , MOV AX, [2001h] A10120h
2. If the addressing mode is indirect then No. of machine cycles = No. of
Words + 1.
E.g. MOV AX,[BX] 8B07h ( Machine cycles = 01+1)
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Instruction Cycle
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Bus Cycle
• MOV AX, BX
• 8B C3
• 1 MEMR (OPCODE FETCH)
Bus Cycle : No of Machine Cycles required for execution of the
Instruction
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Bus Cycle
Bus Cycle : No of Machine Cycles required for execution of the
Instruction
• ADD BX, [0110]
• 03 1E 10 01
• 2 MEMR (OPCODE FETCH)
• i.e. 2 Machine cycles
• To execute the instruction
• 1 Machine cycle---- Read Data from [0110]
• Total 3 Machine Cycles
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Bus Cycle
Bus Cycle : No of Machine Cycles required for execution of the
Instruction
• ADD [0110], BX
• 01 1E 10 01
• To instruction fetch:
• 2 MEMR (OPCODE FETCH )
• 2 Machine cycle
• To execute the Instruction
• 1 Machine cycle---- Read Data from [0110]
• 1 Machine cycle---- Store Results in DS:0110
–(1 MEMW)
• Total 4 Machine Cycles
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Bus Cycle
Bus Cycle : No of Machine Cycles required for execution of the
Instruction
• CBW
• 98
• 1 MEMR (OPCODE FETCH)
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DELAY LOOPS
Certain amount of time or delay is associated with the execution of an
Instruction.
•Thus instruction execution gives us a means of generating a delay .
Consider instructions below,
MOV CX, 100 4 cycles
HERE: LOOP HERE 17/5 cycles
• Total no. of clock cycles required is 4+(100*17) -12 =1692 cycles
•In a system with 12 MHz clock, clock period is .083μ Sec
- Total delay in this case .083 *1692 =140 μ Sec
•It is possible to fix the value of N so as to get a desired value of delay .
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DELAY LOOPS
MOV CX,N 4
HERE: NOP 3
LOOP HERE 17/5
Most of the delay occurs within the loop
the total cycles of delay is =[(3+17) x N]-12.
•
Total delay time =1 m sec =20N x 0.083 μsecs
•
For 1 msec delay ,the value of N =602 or 25AH
•
This value of N is inserted into program to create a delay of 1msec
•
Generating delays in this manner is called software delays.
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MEMORY ACCESS TIME
TCLAV- Time from Clock to Address Valid ; 110 ns for MHz Clock
Memory Access Time : TCLAV time must be subtracted from the three clocking
states (600 ns) separating the appearance of the address (T
1
) and the sampling
of the data (T
3
).
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MEMORY ACCESS TIME
• TCLRL- Time from Clock to Read Line
• TDVCL – Time Data Valid to Clock 30ns
• Memory Access Time : 600 ns-110ns-30ns = 460 ns
• A wait state (T
w
) is an extra clocking period between T
2
and T
3
to lengthen bus
cycle
• On one wait state, memory access time of 460 ns, is lengthened by one clocking
period (200 ns) to 660 ns, based on a 5 MHz clock.
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• Thankyou
